1. Field of the Invention
The present invention is related generally to communications with host adapter integrated circuits, and in particular to methods of queuing hardware control blocks that are used in communicating tasks to one or more host adapter integrated circuits, or other devices.
2. Description of Related Art
Hardware control blocks, sometimes called sequencer control blocks or SCSI control blocks (SCBs), are typically used for transferring information between a software host adapter device driver in a host computer and a host adapter integrated circuit that controls operations of one or more peripheral devices. Methods for queuing SCBs are known to those of skill in the art. For example, see copending and commonly assigned U.S. patent application Ser. No. 07/964,532entitled "Intelligent SCSI Bus Host Adapter Integrated Circuit," of Craig A. Stuber et al. filed on Oct. 16, 1992, which is incorporated herein by reference in its entirety. See also copending and commonly assigned U.S. patent application Ser. No. 08/269,491 entitled "A Sequencer Control Block Array External To A Host Adapter Integrated Circuit" of B. Arlen Young, et al. filed on Jun. 30, 1994, and also U.S. Pat. No. 5,564,023 entitled "Method for Accessing A Sequencer Control Block By A Host Adapter Integrated Circuit" of B. Arlen Young issued on Oct. 8, 1996, each of which is incorporated herein by reference in its entirety.
Typically, the software host adapter device driver, that transmits SCBs to the host adapter integrated circuit, included an operating system specific module (OSM) and a hardware interface module (HIM) that both were maintained in the host computer system. The OSM knew nothing about the hardware in the host adapter integrated circuit and communicated with both the host computer operating system and the HIM. The HIM communicated only with the host adapter integrated circuit and the OSM. The OSM provided information for use in a SCB and sent that information to the HIM, which in turn built a SCB. Alternative methods for queuing the SCBs by the HIM and the host adapter integrated circuit are described in the patents referenced above and so are not repeated herein.
In FIG. 1, an operating system executing on a host computer microprocessor 105, e.g., an Intel Pentium microprocessor, receives a command for a disk drive, e.g., a virtual disk drive read command or a virtual disk drive write command to a RAID system 170, from an application also executing on microprocessor 105. In response to the command, the operating system calls a device driver 103 that includes an OSM 101 and a HIM 102, both of which execute on microprocessor 105.
OSM 101 sends information necessary to implement the command to HIM 102 and in turn transfers control to HIM 102. HIM 102 includes the information received from OSM 101 in a SCB or SCBs, that are built by HIM 102, to implement the command.
HIM 102 manages a plurality of host adapter devices 120, 130, and a buffer memory controller device 140 that are on an I/O bus, which in this embodiment is a PCI bus 111. HIM 102 configures each SCB for execution by a particular one of these devices. PCI bus 111 is coupled to microprocessor 105 by a PCI bus interface circuit 110.
Buffer memory controller device 140 is, for example, an Adaptec AIC 7810 host adapter integrated circuit, while host adapter devices 120 and 130 are each an Adaptec AIC-7880 host adapter integrated circuit. Each of host adapter integrated circuits 120, 130, and buffer memory controller device 140 includes an on-board processor, i.e., sequencers 125, 135 and 145, respectively, and scratch memory 126, 136, and 146, respectively. Each of devices 120, 130, and 140 also includes a queue-in FIFO register 127, 137, and 147, respectively. Each of queue-in FIFO registers 127, 137, and 147 (an hold up to 256 pointers to SCB storage sites in a SCB array 155 stored in an external memory 150. HIM 102 can access memory 150 over bus 111, and through any one of device 120, 130, and 140.
Task requests from HIM 102 to host adapter devices 120, 130, and buffer memory controller device 140 are made via the SCBs. In this embodiment, HIM 102 writes the SCBs to one of 256 sites of SCB array 155 (FIG. 1) in random access memory (RAM) 150. The size of each site is 32 bytes. Each SCB written to a site in RAM 150 is executed by a sequencer in one of devices 120, 130, and 140. Similarly, when execution of the SCB is completed, HIM 102 receives the completed SCB from the site in RAM 150.
Specifically, HIM 102 builds each SCB in memory 104. To deliver a SCB to a device, e.g., host adapter device 120, HIM 102 first pauses the sequencer, e.g., sequencer 125, which halts execution of whatever the sequencer may be processing. After sequencer 125 is paused, HIM 102 transfers the SCB from host memory 104 to a SCB storage site, e.g., SCB site thirty-seven, of a shared SCB array 155 in external memory 150 using a programmed I/O (PIO) over bus 111. HIM 102 also transfers a pointer to the SCB storage site using a PIO transfer over bus 111 to queue-in-FIFO register 127. After the pointer is transferred to queue-in-FIFO register 127, HIM 102 unpauses sequencer 125 so that sequencer 125 can resume execution of the paused process.
When host adapter device 120 is idle, sequencer 125 checks queue-in-FIFO register 127 to determine whether queue-in-FIFO register 127 is empty. If queue-in-FIFO register 127 is not empty, one or more SCBs are in SCB array 155 for execution by host adapter device 120. In this event, sequencer 125 pops a pointer off queue-in-FIFO register 127 and begins execution of the SCB addressed by the pointer. Upon interruption or completion of the execution of the SCB, sequencer 125 checks queue-in-FIFO register 127 again. This sequence of actions is repeated until queue-in-FIFO 127 is empty.
The operations described above for host adapter device 120 are also performed by devices 130 and 140. The PIO transfers of the SCBs and the pointers require a considerable amount of execution time on host microprocessor 105. Also, the device sequencer may be stopped for the PIO transfer at an inconvenient time, which in turn results in noticeable delays on the SCSI bus, e.g., SCSI bus 121 or SCSI bus 131.
Also, in some applications, HIM 102 builds a chain of SCBs to implement a particular virtual disk drive command. See for example, copending and commonly assigned U.S. patent application Ser. No. 08/617,990 entitled "Method for Specifying A Sequence of Execution of I/O Command Blocks In A Chain Structure" of B. Arlen Young filed on Mar. 15, 1996 which is incorporated herein by reference in its entirety.
While chaining provides significant performance advantages, the PIO transfers degrade the performance of host microprocessor 105. One way to remove the performance degradation would be to have each device perform a DMA transfer of the SCBs in the chain that are executed by the device. Use of DMA transfers eliminates the host microprocessor performance degradation associated with the PIO transfers. However, with DMA transfers, as explained more completely below, a race condition can arise when a SCB for a device is transferred to SCB array 155 using that device.
A chain of SCBs cannot begin execution until the head SCB of the chain is executed. However, when the head SCB completes execution, the subsequent SCB or SCBs in the chain that are enabled for execution upon completion of execution of the head SCB must be in SCB array 155.
Unfortunately, it is not possible to predict when the head SCB will complete execution, or when remaining SCBs of a chain will be delivered by any other device to SCB array 155. Consequently, a race condition can develop in system 170 with respect to loading SCBs in a chain into SCB array 155 when each device is responsible for the DMA transfer of the SCBs in the chain that are subsequently executed by that device.
If the possibility of such a race condition could be eliminated, it would assure the functionality of chaining of SCBs. Also, since the operations being performed are typically associated with managing user data, a SCB queue management method that is reliable, and reduces host microprocessor processing time also is desirable. Unfortunately, with the current methods, only PIO transfers can assure that chaining functions correctly and so the processing time on the host microprocessor for the PIO transfers is also necessary.